Subject: RE: Verilog-AMS - Issue 15: `include
From: Tom Fitzpatrick (fitz@co-design.com)
Date: Tue Jul 09 2002 - 12:56:19 PDT
I agree with Steve that it is not a good idea to have multiple syntaxes for
things.
-Fitz
> -----Original Message-----
> From: owner-sv-ec@server.eda.org [mailto:owner-sv-ec@server.eda.org]On
> Behalf Of Steven Sharp
> Sent: Tuesday, July 09, 2002 3:10 PM
> To: sv-ec@server.eda.org
> Subject: Re: Verilog-AMS - Issue 15: `include
>
>
>
> >BTW, would the CPP syntax '#include ...' clash with SystemVerilog? If not
> >could we add it as an alternate syntax? - E.g. lines begining with "`"
> >are treated the same as lines beginning "#".
>
> Presumably Verilog used ` instead of # to avoid parsing problems and/or
> confusion with #delay syntax. The decision has already been made on the
> syntax. I don't see any reason to re-visit it. Nor is it a good idea to
> start adding multiple syntaxes for everything in the language.
>
> Steven Sharp
> sharp@cadence.com
>
>
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