Subject: RE: Verilog-AMS - Issue 15: `include
From: Michael McNamara (mac@verisity.com)
Date: Tue Jul 09 2002 - 13:26:12 PDT
Tom Fitzpatrick writes:
> I agree with Steve that it is not a good idea to have multiple syntaxes for
> things.
>
> -Fitz
>
> > -----Original Message-----
> > From: owner-sv-ec@server.eda.org [mailto:owner-sv-ec@server.eda.org]On
> > Behalf Of Steven Sharp
> > Sent: Tuesday, July 09, 2002 3:10 PM
> > To: sv-ec@server.eda.org
> > Subject: Re: Verilog-AMS - Issue 15: `include
> >
> >
> >
> > >BTW, would the CPP syntax '#include ...' clash with SystemVerilog? If not
> > >could we add it as an alternate syntax? - E.g. lines begining with "`"
> > >are treated the same as lines beginning "#".
> >
> > Presumably Verilog used ` instead of # to avoid parsing problems and/or
> > confusion with #delay syntax. The decision has already been made on the
> > syntax. I don't see any reason to re-visit it. Nor is it a good idea to
> > start adding multiple syntaxes for everything in the language.
> >
> > Steven Sharp
> > sharp@cadence.com
> >
> >
>
I don't like the idea either for the reasons already expressed; and
moreover because "# token" is already well defined in Verilog to mean
a delay. And hence the compiler (and the user) would have to figure
which is what when.
Further, 'include' is not a reserved word, so users could have:
module foo;
reg [31:0] include = 34,
exclude,
preclude;
child stdio();
always @( posedge exclude ) begin
preclude <= #include stdio.h;
end
endmodule
module stdio;
reg [31:0] h = 67;
endmodule
-mac
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