Verilog-AMS - Issue 15: `include


Subject: Verilog-AMS - Issue 15: `include
From: Kevin Cameron x3251 (Kevin.Cameron@nsc.com)
Date: Mon Jul 08 2002 - 17:10:02 PDT


http://www.eda.org/verilog-ams/htmlpages/tc-docs/issues/0015/index.html

I was asked to run this by the SystemVerilog committee.

Does anyone object to using C-like angle brackets for system include
files in a future SystemVerilog (assuming we combine it with Verilog-AMS
- version 4.X! )?

Verilog-A has various bundled header files for constants and disciplines
we would like to identify as different from user files of the same name.

Feedback appreciated,
Kev.

-- 
National Semiconductor
2900 Semiconductor Drive, Mail Stop D3-500, Santa Clara, CA 95052-8090

Issue 15: `include

- + Issue 15: `include

[Kevin Cameron, 01 Dec 2000]


LRM: 11.5 `include

Proposal

Unlike Verilog-D, Verilog-A has "system" include files for default/standard disciplines physical constant values and maybe simulator/tool supported features. As with "C" Verilog-A[MS] should include these with "<>" rather than '"' quotes.

For backward compatibility the system file include path should be appended to the end of the user search path so that system files quoted with '"' will be found (if not overridden).



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