Subject: Re: Verilog-AMS - Issue 15: `include
From: Steven Sharp (sharp@cadence.com)
Date: Tue Jul 09 2002 - 14:40:47 PDT
>> >Actually, 'include' _is_ a reserved word. See Annex B of 1364-2001.
>>
>> Then Annex B is wrong. I just tested this in Verilog-XL, and it isn't
>> reserved. So Mac is right.
>
>I didn't know that Verilog-XL conformed to 1364-2001.
You are correct that it does not. And include is used as a reserved
word in library map files in 1364-2001. However, I believe that those
files use a completely separate grammar from the Verilog source files,
though this may be open to debate. So I would argue that include may
be a reserved word used in one of the grammars in 1364-2001, but not
in the Verilog grammar.
Steven Sharp
sharp@cadence.com
This archive was generated by hypermail 2b28 : Tue Jul 09 2002 - 14:42:21 PDT