Subject: Re: Verilog-AMS - Issue 15: `include
From: Michael McNamara (mac@verisity.com)
Date: Tue Jul 09 2002 - 10:04:11 PDT
Simon Davidmann writes:
> [1 <text/plain; us-ascii (7bit)>]
>
> In C the methodology is all about using header files - and more so
> with C++. In my experience, in Verilog this is not the case
>
I disagree! Good Verilog design strategy very definiatly uses include
files.
Methodology that I used at Ardent, SGI and Chromatic Research as a
both a designer and as a verification engineer had a set of major
include file for each chip in the design; and each top level netlist
file included the right include file(s). Hence:
% head router.v
`include "router.h"
module router(
input clk;
...
% head router.h
`ifdef ROUTER_H
// already included
`else
`define ROUTER_H 1
`define CLK 80
`define BUS_WIDTH 32
...
> What are 'system include' files - in a verilog world what would
> they be for?
I assume what Kevin wants as well is the equivalent of the C
compilers's -I switch, which specifies what directories are seached to
fulfill include <> requests, as it makes no sense for a verilog
compiler to look at a default place like /usr/include/ to find include
files.
Hence I imagine he is implictly proposeing something like:
% verilog -I/bigproject/design/include -f design.f -o bigsim
where design.f has files that do
`include <router.h>
and hence router.h is searched for in /bigproject/design/include for
this compilation.
For a different simulation, he might do:
% verilog -I/smallproject/design/include -f design.f -o smallsim
and get a different set of include files that use the same underlying
design files; but for which BUS_WIDTH may be 16, or CLK might be 40,
for example.
-mac
>
> Simon
>
> At 05:10 PM 7/8/2002, Kevin Cameron x3251 wrote:
>
> >http://www.eda.org/verilog-ams/htmlpages/tc-docs/issues/0015/index.html
> >
> >I was asked to run this by the SystemVerilog committee.
> >
> >Does anyone object to using C-like angle brackets for system include
> >files in a future SystemVerilog (assuming we combine it with Verilog-AMS
> >- version 4.X! )?
> >
> >Verilog-A has various bundled header files for constants and disciplines
> >we would like to identify as different from user files of the same name.
> >
> >Feedback appreciated,
> >Kev.
> >
> >--
> >National Semiconductor
> >2900 Semiconductor Drive, Mail Stop D3-500, Santa Clara, CA 95052-8090<x-html>
> ><BASE HREF="http://www.eda.org/verilog-ams/htmlpag
> >es/tc-docs/issues/0015/index.html">
> >
> >
> ><../0014/index.htm>- <../0016/index.htm>+ <../index.htm#iss15>Issue 15:
> >`include
> >
> >
> >
> >
> >
> >[Kevin Cameron, 01 Dec 2000]
> >
> >
> >
> >
> >
> >
> >LRM:
> ><http://www.eda.org/verilog-ams/htmlpages/tc-docs/lrm/2.0/compdir.html#860362>11.5
> >`include
> >
> >Proposal
> >
> >
> >
> >Unlike Verilog-D, Verilog-A has "system" include files for
> >default/standard disciplines physical constant values and maybe
> >simulator/tool supported features. As with "C" Verilog-A[MS] should
> >include these with "<>" rather than '"' quotes.
> >
> >For backward compatibility the system file include path should be appended
> >to the end of the user search path so that system files quoted with '"'
> >will be found (if not overridden).
> >
> ></x-html>
> [2 <text/html; us-ascii (7bit)>]
>
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