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Low Power Design, Verification, and Implementation with IEEE 1801™ UPF™

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Presenters

Erich Marschner Erich Marschner
Mentor Graphics
Qi Wang Qi Wang
Cadence
John Biggs John Biggs
ARM
Sushma Honnavarra-Prasad Sushma Honnavarra-
Prasad
Broadcom
Jeffrey Lee
Synopsys
   

2/25/13

Low power design and verification are increasingly necessary in today's world, as electronic devices become increasingly portable, power and cooling become increasingly expensive, and consumer demand for more features with less power drive product development. The IEEE 1801 standard, Unified Power Format (UPF), enables low power design and verification in multi-vendor flows, from early RTL verification of the power management architecture through physical design and implementation. This lecture-format tutorial will present an overview of UPF-based low power design, verification, and implementation, as well as examples of UPF application from both the IP developer's and the system integrator's perspective.

This tutorial will cover the basics of Accellera UPF and then focus on the features of IEEE 1801 that enable the description of more sophisticated power management systems. The tutorial will also provide recommendations regarding migration from Accellera UPF to IEEE 1801 and the methodology changes that are required. It will identify some of the changes coming in 2013 to clarify and enhance the semantics of IEEE 1801.

The first half of the tutorial will be a detailed review of UPF and low power design concepts, including a discussion of power management techniques, power management architecture, and power intent specification. This section will cover power architectural elements such as power domains, isolation, level shifting, and retention; power distribution elements such as supply ports and nets, power switches, and supply sets; and power state modeling for supplies, supply sets, power domains, and systems. Methodology for effective use of these features will also be addressed, including the concepts of hierarchical specification of power intent and incremental refinement. This part of the tutorial will be presented by EDA tool developers.

The second half of the tutorial will present a UPF-based design flow highlighting the practical aspects of using UPF for verification and implementation. This section will cover the use of UPF for specification of low power constraints for IP blocks, logical configuration of those blocks for integration into a system, and the system's technology-specific physical implementation. This flow will be illustrated with practical examples representative of real systems. Best practices for successful design and verification of low power systems with UPF will also be presented. This part of the tutorial will be presented by UPF users.

The tutorial is split into seven parts:

  • Part 1: Introduction
  • Part 2: Low Power Design and Verification
  • Part 3: Unified Power Format (UPF)
  • Part 4: Power Intent Specification Methodology
  • Part 5: Using UPF for IP Design
  • Part 6: Using UPF for System Design
  • Part 7: What's New in UPF 2.1


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