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Accellera Day at DVCon US 2015

Accellera Day 2015 at DVCon United StatesAccellera Systems Initiative invites you to a special day dedicated to technical standards at the 2015 Design and Verification Conference in San Jose, CA. Find out the latest in EDA and IP standards being developed and implemented by today’s leading electronics companies. Accellera Day tutorials throughout the day will primarily focus on design issues including practical examples of SystemVerilog for design, examples and new standards work for SystemC, and even methods to apply UCIS for tracing design requirements.

  • SystemVerilog Design: User Experience Defines Multi-tool, Multi-vendor Language Working Set will bring together leading edge technology users who have used SystemVerilog constructs in their design. They will describe their motivations for using SystemVerilog, the success and failures they encountered along the way, and the productivity gains achieved. The tutorial will be delivered by experts through real code, real examples, and real improvements that were achieved on the way to tape out. 
  • Automating Design and Verification of Embedded Systems Using Meta-Modeling and Code Generation Techniques presents the application of the SW development methodology "Meta-Modeling and Code Generation" to the design of SOCs, mainly the semi-automated generation of SystemC prototypes, firmware and hardware as well as verification measures such as elements of a SystemVerilog UVM testbench.
  • Next Generation Design and Verification Today will walk through a methodology that uniquely uses the power and architecture of the SystemVerilog UVM_REG to provide the necessary hooks to achieve constrained random stimulus during an AMS simulation thereby allowing the verification engineers to collect coverage automatically. Specific examples and lessons learned will be shared to emphasize how these techniques help in bridging the coverage gap between analog and digital interfaces which are the most challenging areas in the realm of mixed-signal verification.
  • SystemC Standardization Update Including UVM for SystemC will cover how Accellera member companies are evolving the IEEE 1666 SystemC standard to combat the ever-increasing complexity of electronic systems. The tutorial will provide user experiences applying SystemC and a glimpse of the future in the areas of analog modeling, a synthesizable subset, model-tool interface, and verification.

Our Sponsored Luncheon continues the Accellera Day theme of bringing the Design back to DVCon. The luncheon features a panel discussion titled "What Is Needed to Drive Design Efficiency?" that will be moderated by John Aynsley. The panel's technical experts will discuss current practices and gaps with a focus on where the standards need to go. In addition, Accellera will present its annual Technical Excellence Award for outstanding achievement and contribution to Accellera standards.

Join us at this day-long event to connect with experts and users as we learn, share, and network on the latest in standards innovations!


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Recent Happenings


• Article: DVCon 2015: Not to be Missed by Gabe Moretti


• New Portable Stimulus Working Group


February newsletter now available


• UVM 1.2 released. Download | Read the press release


• Yatin Trivedi receives 2014 Accellera Leadership Award


• Verilog-AMS 2.4 released. Download | Read the press release




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Download the latest Accellera Systems Initiative standards:


IP-XACT Vendor Extensions

OCP 3.0

OVL 2.8.1

SCE-MI 2.2

Soft IP Tagging 1.0

SystemC (Includes TLM)

SystemC AMS 2.0

UCIS 1.0

UVM 1.2

Verilog-AMS 2.4


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