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DAC 2009
Breakfast and Panel Discussion: "Frontiers in Verification: Coverage, Closure and Beyond" Moderator: Scott Sandler, vice president of corporate marketing, SpringSoft Verification of complex electronic system and IC designs is a constantly and rapidly evolving art. Changes in how designs are constructed at the silicon, circuit, logic, and system levels demand new tools and tactics. The implications for verification are enormous: IP plays an increasing role, standards are essential to ensure interoperability of tools, and issues such as coverage, closure, power, and software are becoming critical. This panel will bring together a group of verification professionals for a lively conversation on how verification must change in the coming years to keep pace.
Tuesday, July 28, 2009 IEEE 1801: Celebrating Success of Low Power User Community with UPF Accellera's UPF is now the IEEE 1801 Standard for low power design and verification. Several users have successfully deployed the use of UPF in their design and verification methodology. Listen to the insightful presentations from real users on their experiences with using UPF; where they saw benefits, some of the future challenges, and how the standard needs to grow in order to continue driving the methodology of tomorrow’s low power devices.
We will also celebrate the efforts of the team that worked so hard on creating the IEEE 1801 standard. Boxed lunch will be served; please register for this event here.
Tuesday, July 28, 2009 SystemVerilog Is Getting Even Better! Verification and design engineering teams worldwide have rapidly adopted the SystemVerilog-2005 standard and found SystemVerilog to be beneficial for delivering working, well tested products in an efficient and timely manner. The IEEE SystemVerilog standards group has continued to improve SystemVerilog, based on feedback and requests from engineers who are using the standard, and from companies implementing SystemVerilog tools. This presentation provides an overview of more than 50 major new features being added in the proposed SystemVerilog-2009 standard. Many of these new features are substantial, and improve the ability to accurately and efficiently model and verify extremely complex digital designs. The presenters are Cliff Cummings of Sunburst Design and Stuart Sutherland of Sutherland HDL. Both presenters are experts in SystemVerilog and are renown for providing dynamic and informative presentations and tutorials. DON'T MISS THIS
Tuesday, July 28, 2009 Accellera is the leading standards organization developing language-based standards used by system, semiconductor, Intellectual Property (IP) and EDA companies. The SPIRIT Consortium is the leading standards organization focused on developing standards for IP deployment and reuse. Sponsored by Cadence, Denali, and Synopsys
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