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About Verilog-AMS

Mission Statement

Develop and promote a Verilog-AMS standard in a timely fashion and pass it off to the IEEE. The standard will include: Analog extensions to Verilog, Mixed-Signal extensions to Verilog, and AMS extensions to the Verilog PLI 2.0. Develop a validation suite to measure compliance with the standard. Track and adjust to the changes in IEEE 1364 Verilog to ensure future compatibility with the digital language.

Overview

The Verilog-AMS Hardware Description Language (HDL) language defines a behavioral language for analog and mixed signal systems. Verilog-AMS HDL is derived from the IEEE 1364 Verilog HDL specification. The Verilog-AMS technical committee is responsible in the creation, definition and semantics of Verilog-AMS HDL as proposed by Accellera Systems Initiative.

The intent of Verilog-AMS HDL is to let designers of analog and mixed signal systems and integrated circuits create and use modules that encapsulate high-level behavioral descriptions as well as structural descriptions of systems and components. The behavior of each module can be described mathematically in terms of its terminals and external parameters applied to the module. The structure of each component can be described in terms of interconnected sub-components. These descriptions can be used in many disciplines such as electrical, mechanical, fluid dynamics, and thermodynamics.

Verilog-AMS HDL is defined to be applicable to both electrical and non-electrical systems description. It supports conservative and signal-flow descriptions by using the terminology for these descriptions using the concepts of nodes, branches, and ports. The solution of analog behaviors which obey the laws of conservation fall within the generalized form of Kirchhoff's Potential and Flow laws (KPL and KFL). Both of these are defined in terms of the quantities associated with the analog behaviors.

Verilog-A

Prior to the release of Verilog-AMS, the Accellera board approved an analog-only specification called Verilog-A. With the release of Verilog-AMS the "official" Verilog-A LRM will no longer be supported as it is included as part of the Verilog-AMS specification. Annex C in the Verilog-AMS LRM is provided to help developers define a working subset of Verilog-AMS HDL for analog only products. Products based on the Verilog-A subset are encouraged as there are many applications requiring just this subset.

Analog language features

The Verilog-A subset provides a unique set of features over the digital modeling language (IEEE 1364, Verilog Hardware Description Language, henceforth called Verilog-D) to provide a analog specific language based on the Verilog-D language for compatibility. Below is a list of salient features of the resulting analog subset:

  • Verilog-A modules are upward compatible with Verilog-AMS
  • Analog behavioral description are contained in separate analog block
  • Branches can be named for easy selection and access
  • Parameters can be specified with valid range limits
  • Control of the simulation time step for accurate simulation
  • Full set of mathematical functions and operators for describing analog behavior
  • Time Derivative and Integral Operators
  • Modeling of white, flicker, frequency dependent noise
  • Waveform filters to modify input signal including:
  • Sample Data systems with Z-domain filters
  • Linear continuous time filters with Laplace Transforms
  • Waveform smoothing filters for discrete and continuous signals
  • Event and Analysis detection

Mixed-signal language features

The Verilog-AMS extends the features of the digital modeling language (IEEE 1364, Verilog-D) and Verilog-A to provide a single unified language with both analog and digital semantics with backward compatibility. Below is a list of salient features of the resulting language:

  • Signals of both analog and digital types may be declared in the same module
  • Signals can be of type real
  • initial, always, and analog procedural blocks may appear in the same module
  • Both analog and digital signal values may be accessed (read operations) from any context (analog or digital)
  • Digital signal values may be set (write operations) from any context outside of an analog procedural block
  • Analog signals may only receive contributions (write operations) from inside an analog procedural block
  • The semantics of the initial, always, and analog procedural blocks remain unchanged
  • The discipline declaration is extended to digital signals
  • A new construct, connect statement, is added to facilitate auto-insertion of user defined connection modules between the analog and digital domains
  • When hierarchical connections are of mixed type (i.e. analog signal connected to digital port or digital signal connected to analog port) then user defined connection modules are automatically inserted to perform signal value conversion

Natures, disciplines and nodes

Verilog-AMS HDL allows definition of nodes based on disciplines. The disciplines associate potential and flow natures for conservative systems or only potential nature for signal-flow systems. The natures are a collection of attributes, including user-defined attributes, that describes the units (meter, gram, newton, etc.), absolute tolerance for convergence, and the names of potential and flow access functions. Many nodes can share the same disciplines and natures. The compatibility rules help enforce the legal operations between nodes of different disciplines. For Verilog-AMS the discipline feature has been extended to support discrete as well as continuous domains allowing for the automatic insertion of interface elements.