Design & Verification Conference and Exhibition
DVCon United States
DVCon United States offers the industry’s most comprehensive technical program focused on the design and verification of electronics systems. The four-day conference kicks off with "Accellera Day," a day filled with information-packed technical tutorials focused on design challenges and the future of efficient design. In addition to in-depth technical sessions, posters and panels throughout the conference, an industry Expo provides an opportunity to meet with vendors and get demos targeted at specific design and verification challenges. DVCon is an excellent opportunity to meet with experts, colleagues and users to share ideas and get the latest information on what’s developing in the industry.
- Audience. DVCon attracts engineers and industry technologists from around the world across many design disciplines including systems, standard IC, ASIC, DSP, microprocessor, FPGA, library, analog-mixed signal and SoC.
- Gain insight from users on standards and languages. DVCon selects the best user experiences, high quality papers and presentations around best practices on the application of standardized languages, tools and methodologies for design and verification such as SystemC, SystemVerilog, PSL, UVM, IP-XACT and many more.
- Learn from the experts. DVCon organizes technical workshops and tutorials on emerging EDA and IP standards, with highly educational content. Experts in the industry share on topics like UVM, SystemC and IP-XACT, with the fundamental concepts and practical usage of these standards explained, including examples and demonstrations.
- Connect to standardization developments. DVCon is hosted by Accellera Systems Initiative, the recognized organization with the mission to develop and deploy EDA and IP standards. Experts are available to discuss standards development and user needs.
- Network with peers. DVCon is the place to meet experts from various industries and connect with peers to discuss the latest practices and trends in design and verification. Join us at networking events to interact with colleagues, share techniques and learn how other users tackle the challenges.
- Find out the latest EDA and IP vendor offerings. DVCon hosts a compact exhibition where the industry can meet to discuss EDA and IP tool and service solutions. Visit the exhibition for demonstrations, interactive discussions and top vendor offerings.
DVCon Europe is a technical conference in Europe targeting the application of standardized languages, tools, and methodologies for the design and verification of electronic systems and integrated circuits. In order to boost the interest, usage and development of electronic design automation (EDA) and intellectual property (IP) standards in Europe, this highly technical conference is organized to invite industry experts to learn and share best practices on:
- The application of system-level design and verification languages such as SystemC, SystemVerilog or e
- The use of SystemVerilog Assertions (SVA) or the Property Specification Language (PSL)
- Verification methodologies based on the Universal Verification Methodology (UVM)
- IP reuse, automation and integration standards based on IP-XACT
- Low power design and verification using the Unified Power Format (UPF)
General topic areas on Electronic System Level (ESL), Verification & Validation, Analog/Mixed-Signal, IP reuse, Design Automation, and Low Power design and verification, will be highlighted in tutorials, papers, and poster sessions. With a highly technical focus on System and IC design, verification, and integration, DVCon Europe is a very practical and industry-focused conference on EDA standards and standardization. Conference attendees are primarily designers of electronic systems, ASICs and FPGAs, as well as those involved in the research, development and application of EDA tools and IP integration.
DVCon India provides an excellent platform to share knowledge, experience and best practices covering Electronic System Level Design & Verification for IP and SOC, VIP development and Virtual Prototyping for Embedded Software development and debug.
The conference provides multiple opportunities to interact with industry experts delivering keynote speeches, invited talks, tutorials, panel discussions, technical paper presentations, poster sessions and exhibits from ecosystem partners. The attendees also get the latest information on various Accellera standards for system design, modelling and verification. These standards include UVM, SystemC (and its variants like SystemC-AMS, SCV, CCI, Synthesis subset), SystemVerilog, PSL, Assertions for AMS, Verilog, IP-XACT, OCP and many more.
The 2-day event is attended by industry leaders, system architects, verification experts, SoC integrators, chip designers, IP developers, VIP developers and firmware engineers. The conference has two parallel tracks:
- ESL Track: SystemC related topics such as Pre-Si SW development and debug using virtual prototypes of electronic systems and SoCs, architectural exploration, power and performance analysis for use cases, high level synthesis, model interoperable standards and more.
- DV Track: Design & Verification languages, methodologies based on SystemVerilog, Verilog, UVM and technologies such as Formal Verification, Hardware Acceleration, Emulation and prototyping, along with the most widely used simulation and more.
DVCon India extends a unique opportunity to engineers at all levels to learn, share and network with each other.