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systemc-forum - [Systemc-forum] Problem in integeration systemC with verilog wrapper Message Thread: Previous | Next
  • To: <systemc-forum@xxxxxxxxxxx>
  • From: <antonyraj.pichai@xxxxxxxxx>
  • Date: Fri, 24 Jun 2005 09:31:00 +0530
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hi,    

I have the problem when i integerate  the systemC code with verilog
code.This occurs when i did the modifications in systemC ports
declaration.The modifications as follows,

    previous code

   SC_MODULE(transport)

{

 sc_in<bool> h_reset_66_n; // Hard Reset

sc_in<bool> hsel; // Transport Block select

sc_out<sc_uint<32> > hrdata; // Read data

sc_out<bool> hready; // ready signal to complete the access

SC_CTOR{

}

};

Now we modified by grouping the IN Ports in a seperate structure and OUT
Ports in seperate structure

like

SC_MODULE(transport)

{

AHBINPORTS  stAhbInPorts;

AHBOUTPORTS stAhbOutPorts;

SC_CTOR(transport):

 stAhbInPorts.h_reset_66_n("stAhbInPorts.h_reset_66_n"),

   similarly output ports.

} This works fine with systemC alone.

when I integrate  with verilog wrapper like below in verilog code

   .stAhbInPorts.h_reset_66_n(h_reset_66_n);

   the compiler issuing error

   ncvlog: *E,ILLHIN (../tb/wpr_sata_trn/verilog/top_tb.v,498|41):
illegal location for a hierarchical name (stSystemPorts).
                           .stAhbInPorts.h_reset_66_n(h_reset_66_n),

     I want to clarify that do verilog accepts instantiation connecting
to the ports.

  regards 

Antony
                                       







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