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systemc-forum - Re: [Systemc-forum] SystemC timing doubt
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- From: Sandeep S Srinivasa <sss@xxxxxxxxxxxxxxxxx>
- Date: Tue, 06 Jul 2004 20:32:23 +0530
- Cc: systemc-forum@xxxxxxxxxxx
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hi,
Why dont you declare an event say "event1" and do
"event1.notify(SC_ZERO_TIME)" in update_foo,
as well as a "wait(event1)" in issue_foo.
This will cause update_foo and issue_foo to be separated by one delta cycle.
regards
Sandeep
Sadagopan Srinivasan wrote:
Hi,
I have two functions which are sensitive to positive edge of clock.
void emif::update_foo()
{
if(foo_var > 0)
foo_var--;
}
void emif::issue_foo()
{
if(foo_var == 0)
issue_command();
}
The implementation requirement is that update_foo should update in
cycle X and issue_foo should see the change in cycle X+1. Since
systemC has two phases of evaluation and update is it taken care of by
itself normally or should I issue a dummy delay as follows.
void emif::update_foo()
{
wait(SC_ZERO_TIME);
if(foo_var > 0)
foo_var--;
}
this will delay the update of the foo till the end of cycle and so the
issue_foo won't see the value until next cycle.
Cheers,
Sada
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