[sv-ec] [system-verilog] synthesis query for default value of bit type

Hi,
 
What is default value of bit for synthesis in below example?
module test (input  in1, in2,
             output reg   out2);
   bit  a, b;          
   logic  c = a + b;   // c is immune to change of values of a and b as
it is an initialization.
Ques1. What is the default value of a or b considered during synthesis
in this example?
   always@(in1 <mailto:always@(in1>  or in2)
    begin
        a = in1 ;
        b = in2 ;
       out2 = c;   // c = 0 + 0 [== 0]
    end
endmodule
 
Regards,
Prakash



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