Hi Prakash, As discussed in other thread, initial values are to be ignored in Synthesis as a general accepted norm in ASIC synthesis process. Also since the 2-state modeling is more for simulation/perf modeling/higher level abstract models, for synthesis I don't see much of a difference atleast in this example. There are some interesting cases with "optimization exploiting don't cares" that may affect bit/logic/reg mixed usage in RTL and their treatment by synthesis tools, but I have not given lot of thought yet on that. Maybe it is time to start working on SV for Synthesis LRM a la IEEE 1364.1. Does anyone know if such an activity exists or being planned? Regards Ajeetha, CVC www.noveldv.com On Fri, Jan 23, 2009 at 9:36 PM, Prakash Barnwal <pbarnwal@magma-da.com> wrote: > Hi, > > What is default value of bit for synthesis in below example? > module test (input in1, in2, > output reg out2); > bit a, b; > logic c = a + b; // c is immune to change of values of a and b as it > is an initialization. > Ques1. What is the default value of a or b considered during synthesis in > this example? > always@(in1 or in2) > begin > a = in1 ; > b = in2 ; > out2 = c; // c = 0 + 0 [== 0] > end > endmodule > > Regards, > Prakash > > -- > This message has been scanned for viruses and > dangerous content by MailScanner, and is > believed to be clean. > This email was Anti Virus checked by Astaro Security Gateway. > http://www.astaro.com > -- Ajeetha Kumari * A Pragmatic Approach to VMM Adoption * SystemVerilog Assertions Handbook * Using PSL/SUGAR Design Verification Consultant, Contemporary Verification Consultants Private Limited, Bangalore, India, http://www.noveldv.com -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.Received on Fri Jan 23 09:41:49 2009
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