Re: [sv-ec] RE: [system-verilog] synthesis query for byte/logic initial value

From: Ajeetha Kumari <ajeetha_at_.....>
Date: Fri Jan 23 2009 - 09:27:52 PST
Hi Prakash,
   A standard RTL design practice (atleast for ASICs, but as David
points, safer for FPGAs too) is not to rely on such initialization,
instead model proper reset behavior. That said, I believe regular
synthesis users/RTL designers will be OK with such a behavior even for
SV, maybe tool should emit warning/error. Also a potential lint check
for tools like SpyGlass.

HTH
Ajeetha, CVC
www.noveldv.com

On Fri, Jan 23, 2009 at 5:30 PM, Prakash Barnwal <pbarnwal@magma-da.com> wrote:
> Hi Shalom,
>
> Thanks alot for this useful information. I need to know your view for below
> initialization port initialization case.
> In this case , output port result is initialized with factorial_10 (which is
> 2). Does synthesis tool use this information or put output port result as
> floating ?
>

-- 
Ajeetha Kumari
  * A Pragmatic Approach to VMM Adoption
  * SystemVerilog Assertions Handbook
  * Using PSL/SUGAR
Design Verification Consultant,
Contemporary Verification Consultants Private Limited,
Bangalore, India, http://www.noveldv.com

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Received on Fri Jan 23 09:28:34 2009

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