On Fri, Jan 23, 2009 at 6:12 AM, Bresticker, Shalom <shalom.bresticker@intel.com> wrote: > As far as I know, synthesis tool ignore initial assignments to variables, > just like they ignore initial procedures. (Assuming it does not cause a > fatal error.) Just to add fuel to this fire, FPGA synthesis tools may indeed consider initial values on variables, as the initial bitstream load is capable of such initialization even in the absence of any reset. I would not recommend this practice, as there would be no way to re-initialize the FPGA without reloading the bitstream. Instead, design with proper resets. ASIC tools ought to reject this out of hand since there is no common hardware equivalent of an initial assignment. (I can foresee a flip-flop that due to some funky analog power-up bias will always initialize to a known value, and synthesis tools savvy enough to infer these for constant initializations, but I am not aware of anyone actually doing this.) -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.Received on Fri Jan 23 05:36:35 2009
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