[sv-ec] RE: [system-verilog] synthesis query for byte/logic initial value

Hi,

There is no standard synthesis LRM and this standards committee is not responsible for synthesis, but I'll answer you anyway.

As far as I know, synthesis tool ignore initial assignments to variables, just like they ignore initial procedures. (Assuming it does not cause a fatal error.) Unless they appear inside procedural blocks, in contrast to your examples.

So in Testcase 1, the initial value of b would be ignored.

In Testcase 2, some tools might allow initial values to const variables and treat them as similar to parameters, but the initialization of l to the value of i would have the same problem as b in Testcase 1. Besides, I don't think the language guarantees that first i is initialized and then l.

Shalom

________________________________
From: owner-sv-ec@server.eda.org [mailto:owner-sv-ec@server.eda.org] On Behalf Of Prakash Barnwal
Sent: Friday, January 23, 2009 12:15 PM
To: sv-ec@server.eda.org
Subject: [sv-ec] [system-verilog] synthesis query for byte/logic initial value

Hi,

I have a query related to byte/logic initial value.
Could you please reply to below queries?

Testcase1.
module test10 (input [3:0] in1, in2,
             output reg [3:0] out1, out2);
   byte b = { 1'b1, 1'b0,  1'b1, 1'b0,  1'b1, 1'b0,  1'b1, 1'b0 }; // initialize b

Ques1. Does system verilog synthesis's LRM allow to consider initial value of byte b during synthesis ?
  always@(in1<mailto:always@(in1> or in2)
    begin
        out1 = b | in2 - in1;
    end
   always @(b)// should not fire this block
    begin
        out2 = in1 & in2;
    end
endmodule
Testcase2.
module test (input in1,
             output reg out1);

    const int i = 10;    // constant declared with 'const'
    logic [7:0] l = i;   // initialized with the 'const' value
Ques2. Does system-verilog synthesis's LRM allow to consider initial value of logic l (which is 10) during synthesis ?
    always@(*)
    begin
        if (i == l)
        begin
            out1 = in1 ;
        end
        else
        begin
            out1 = 0;
        end
    end
endmodule

Regards,
Prakash


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