[sv-ec] [system-verilog] synthesis query for byte/logic initial value

Hi,
 
I have a query related to byte/logic initial value.
Could you please reply to below queries?
 
Testcase1.
module test10 (input [3:0] in1, in2,
             output reg [3:0] out1, out2);
   byte b = { 1'b1, 1'b0,  1'b1, 1'b0,  1'b1, 1'b0,  1'b1, 1'b0 }; //
initialize b
 
Ques1. Does system verilog synthesis's LRM allow to consider initial
value of byte b during synthesis ?
  always@(in1 or in2)
    begin
        out1 = b | in2 - in1;
    end
   always @(b)// should not fire this block
    begin
        out2 = in1 & in2;
    end
endmodule

Testcase2.
module test (input in1,
             output reg out1);
 
    const int i = 10;    // constant declared with 'const'
    logic [7:0] l = i;   // initialized with the 'const' value
Ques2. Does system-verilog synthesis's LRM allow to consider initial
value of logic l (which is 10) during synthesis ?
    always@(*)
    begin
        if (i == l)
        begin
            out1 = in1 ;
        end
        else
        begin
            out1 = 0;
        end
    end
endmodule
 
Regards,
Prakash


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