[sv-ec] RE: [system-verilog] synthesis query for default value of bit type

By the way, some synthesis tools connect undriven signals or at least undriven inputs, by default, to 0.

Shalom

________________________________
From: owner-sv-ec@server.eda.org [mailto:owner-sv-ec@server.eda.org] On Behalf Of Prakash Barnwal
Sent: Friday, January 23, 2009 6:06 PM
To: sv-ec@server.eda.org
Subject: [sv-ec] [system-verilog] synthesis query for default value of bit type

Hi,

What is default value of bit for synthesis in below example?
module test (input  in1, in2,
             output reg   out2);
   bit  a, b;
   logic  c = a + b;   // c is immune to change of values of a and b as it is an initialization.
Ques1. What is the default value of a or b considered during synthesis in this example?
   always@(in1<mailto:always@(in1> or in2)
    begin
        a = in1 ;
        b = in2 ;
       out2 = c;   // c = 0 + 0 [== 0]
    end
endmodule

Regards,
Prakash


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