RE: [sv-ec] RE: [system-verilog] synthesis query for default value of bit type

IMHO, the only thing that was a flop about 1364.1 was that synthesis
capabilities evolved, but neither the IEEE nor Accellera were willing to
invest in keeping 1364.1 up to date with user needs and tool capabilities.
It wasn't the standard that was a flop, it was the standards bodies.  I
think there is an urgent need for an 1800 synthesis subset, or least an
official recommendation for a subset.  Just my opinion.I fully acknowledge
that others feel differently, and don't think there is any value to debating
who's opinion is more correct, so this will be my only post on this thread.
This is one of those issues where there can be more than one right answer.

 

Stu

~~~~~~~~~~~~~~

Stuart Sutherland

stuart@sutherland-hdl.com

(503) 692-0898

 

From: owner-sv-ec@eda.org [mailto:owner-sv-ec@eda.org] On Behalf Of
Bresticker, Shalom
Sent: Saturday, January 24, 2009 10:25 PM
To: Prakash Barnwal; sv-ec@server.eda.org
Subject: [sv-ec] RE: [system-verilog] synthesis query for default value of
bit type

 

By the way, some synthesis tools connect undriven signals or at least
undriven inputs, by default, to 0.

 

Shalom

 

  _____  

From: owner-sv-ec@server.eda.org [mailto:owner-sv-ec@server.eda.org] On
Behalf Of Prakash Barnwal
Sent: Friday, January 23, 2009 6:06 PM
To: sv-ec@server.eda.org
Subject: [sv-ec] [system-verilog] synthesis query for default value of bit
type

Hi,

 

What is default value of bit for synthesis in below example?

module test (input  in1, in2,
             output reg   out2);

   bit  a, b;          

   logic  c = a + b;   // c is immune to change of values of a and b as it
is an initialization.

Ques1. What is the default value of a or b considered during synthesis in
this example?

 <mailto:always@(in1>    always@(in1 or in2)
    begin
        a = in1 ;
        b = in2 ;

       out2 = c;   // c = 0 + 0 [== 0]
    end

endmodule

 

Regards,

Prakash

 


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