[sv-ec] Query regarding Macro substitution

Hi,

LRM is not clear about how "``" will be interpreted within escaped
identifier.
I have the  query on how the macros defined in the following testcase will
look like after substitution.

Thanks
Kausik


Kausikd: cat mag1.v 

`timescale 10s/100ns

`define X(f) \m[ake_``sd    

`define Y    \m[ake_``sd    

module M;

    `X(kd) I1();
    `Y     I2();

endmodule


Output of VCS is as follows, but I think that is not correct:

Kausikd: cat output.v 

`timescale 10 s / 100 ns
module M;

        \m[ake_sd  I1();
        \m[ake_``sd  I2();
endmodule