Re: [sv-ec] Query regarding Macro substitution

>From: "Kausik Datta" <kausikd@cal.interrasystems.com>

>LRM is not clear about how "``" will be interpreted within escaped
>identifier.

Well, the behavior is already defined in Verilog.  If SV is supposed
to be backward compatible with Verilog, then it should get the same
answer as Verilog (even though that may not be what would be preferred).

An escaped identifier includes all characters up until the next
white space, and that includes ` characters.  Verilog will treat
the `` in both of your examples as part of the escaped identifier.
If SV is backward compatible with Verilog, then it will also treat
them as part of the escaped identifier, not as a token pasting
operation.  Otherwise it would get a different result than Verilog
for existing code.  This means that you cannot use a `` to paste
together two tokens to create an escaped identifier (which could
be an inconvenient limitation).

From your example VCS output, it looks like they are trying to
treat the `` as a token pasting operation, but only inside a macro
that has an argument.  The logic is presumably that token pasting
is only really useful if you have a macro argument to paste onto
an identifier.  If there are no arguments, then it follows the rules.
Or maybe there isn't any logic, and this inconsistent behavior is
just an accident in their code.

Steven Sharp
sharp@cadence.com