Subject: Re: Verilog-AMS - Issue 15: `include
From: Michael McNamara (mac@verisity.com)
Date: Tue Jul 09 2002 - 13:12:19 PDT
Kevin Cameron x3251 writes:
>
> > Simon Davidmann writes:
> > > [1 <text/plain; us-ascii (7bit)>]
> > >
> > > In C the methodology is all about using header files - and more so
> > > with C++. In my experience, in Verilog this is not the case
> > >
> >
> > I disagree! Good Verilog design strategy very definiatly uses include
> > files.
> >
> > Methodology that I used at Ardent, SGI and Chromatic Research as a
> > both a designer and as a verification engineer had a set of major
> > include file for each chip in the design; and each top level netlist
> > file included the right include file(s). Hence:
> >
> > % head router.v
> > `include "router.h"
> > module router(
> > input clk;
> > ...
> >
> > % head router.h
> > `ifdef ROUTER_H
> > // already included
> > `else
> > `define ROUTER_H 1
> > `define CLK 80
> > `define BUS_WIDTH 32
> > ...
> >
> >
> > > What are 'system include' files - in a verilog world what would
> > > they be for?
> >
> > I assume what Kevin wants as well is the equivalent of the C
> > compilers's -I switch, which specifies what directories are seached to
> > fulfill include <> requests, as it makes no sense for a verilog
> > compiler to look at a default place like /usr/include/ to find include
> > files.
> >
> > Hence I imagine he is implictly proposeing something like:
> >
> > % verilog -I/bigproject/design/include -f design.f -o bigsim
> >
> > where design.f has files that do
> > `include <router.h>
> >
> > and hence router.h is searched for in /bigproject/design/include for
> > this compilation.
>
> Unfortunately it's more subtle than that. I created some files -
>
> test1.c:
>
> #include "fnctl.h"
> main () { return O_RDWR;}
>
> test2.c:
>
> #include <fnct.h>
> main () { return O_RDWR;}
>
> And tried these commands -
>
> echo "#define O_RDWR 99" > fcntl.h
> gcc test1.c ; a.out ; echo $status
> # - prints 99
> gcc test2.c ; a.out ; echo $status
> # - prints 2
> gcc test2.c -I. ; a.out ; echo $status
> # - prints 99
> rm fcntl.h
> gcc test1.c ; a.out ; echo $status
> # - prints 2
You need to type
% gcc -nostdinc -I. foo.c
to have gcc forget the wired in "/usr/include" default seatch path.
Ref:
-nostdinc
Do not search the standard system directories for
header files. Only the directories you have speci-
fied with `-I' options (and the current directory,
if appropriate) are searched.
By using both `-nostdinc' and `-I-', you can limit
the include-file search file to only those directo-
ries you specify explicitly.
>
>
> Anyway, I'm not desperate to pin down the semantics at the moment, I'd
> just like to know if folks have any objections to us introducing that
> syntax for Verilog-AMS (assuming the languages combine later in an IEEE
> or Accellera standard).
>
> Kev.
>
> > For a different simulation, he might do:
> >
> > % verilog -I/smallproject/design/include -f design.f -o smallsim
> >
> > and get a different set of include files that use the same underlying
> > design files; but for which BUS_WIDTH may be 16, or CLK might be 40,
> > for example.
> >
> > -mac
>
>
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