Re: [sv-ec] RE: [sv-bc] RE: [sv-ac] New keywords in SV-AC proposals

From: Gordon Vreugdenhil <gordonv_at_.....>
Date: Fri Mar 14 2008 - 01:04:42 PDT
I think that we already have some other systf routines now
(ie. $signed) that I don't think can be written by users
since they have polymorphic return types.  So I think that
some of the systf routines are "more equal" than others
and it would be unsurprising to me if implementations made
restrictions in that space.  Implementation restrictions
in terms of interactions between "legacy" Verilog assumptions
are likely inevitable to some degree.

I think that part of Steven's comments relate to whether we
should be  considering whether a "non-overridable" systf should
even *be* a systf.  I agree with that sentiment but think that
overturning the precendent is likely not worth the level of change.
I do think that we should be very careful in trying to avoid
use of systf forms for things that really cannot be written
as user code.

Gord


Bresticker, Shalom wrote:
> Hi, 
> 
>> I assume that users can define system functions with no 
>> arguments, and that the syntax for a call to such a system 
>> function would not need to have parentheses.  
> 
> The LRM implies that it is allowed.
> 
>> If a user 
>> defined such a system function named $inferred_clock, then 
>> the syntax $inferred_clock used in an expression would refer 
>> to that system function, not to the special meaning in this 
>> proposal.  That seems like a problem.
> 
> I don't think so. The number of user-defined system tasks and functions
> is orders of magnitude less than the number of user-defined identifers.
> 
> Shalom
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Gordon Vreugdenhil                                503-685-0808
Model Technology (Mentor Graphics)                gordonv@model.com


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Received on Fri Mar 14 01:06:47 2008

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