Date: Mon Nov 27 2006 - 00:59:26 PST
Mantis 210 says, Some design styles at Freescale would benefit from the ability to include or not include ports on a module at elaboration time based on the value of a parameter or parameter override. Extending the generate construct to apply to port lists as well as module bodies seems like a good way to do this. Here's an example of what I'm proposing: module foo #(parameter flag=0) ( generate if (flag ==1) input x; endgenerate ); ... endmodule I did not submit Mantis 210. I think. To the best of my recollection, I did not even know about it. But I fully agree with the need. Both at Freescale and at Intel, the need for conditional (and multiple) ports has come up time and again. I'd like to solicit thoughts and suggestions that I can work up into a proposal. Thanks, Shalom Shalom Bresticker Intel Jerusalem LAD DA +972 2 589-6852 +972 54 721-1033
