RE: [sv-bc] Mantis 210: allow use of generate in port list

How would these ports be named? 1364 says that objects in unnamed
generate blocks, as in this example, cannot be accessed from outside the
generate block. Can I do this:
 
 module foo #(parameter flag=0)
 ( generate
     if (flag ==1) begin : blk
       input x;
   end
   endgenerate
  );
if (flag == 1)  
   wire w = blk.x;

endmodule
 
There is also the question of port binding during elaboration. In System
Verilog some port binding must take place before generate unrolling. For
example:
 
interface itf #(width = 8) ();
typedef logic [width-1:0]  IT;
endinterface
 
module m (itf i);
typedef  i.IT  IT;
for (genvar i = 0; i < $bits(IT); i++) begin: blk
...
end
...
endmodule
 
module top;
itf #(16) i;
m u1(i);
endmodule
 
To unroll the generate blocks in module 'm', we have to bind the
interface port 'i' in the module hierarchy and find the actual
instantiation of the interface 'itf', so that we can correctly evaluate
the width of the type 'IT'. This imposes restrictions on generated port
lists and positional port binding at module instantiation.
 
I guess, if generated ports were restricted to the end of the port list
and typedefs that extract types from interface ports were only allowed
for non-generated interface ports, I guess that would be enough.


________________________________

	From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org] On Behalf
Of Bresticker, Shalom
	Sent: Monday, November 27, 2006 12:59 AM
	To: sv-bc@eda.org
	Subject: [sv-bc] Mantis 210: allow use of generate in port list
	
	
	  

	Mantis 210 says,

	Some design styles at Freescale would benefit from the ability
to include or not include ports on a module at elaboration time based on
the value of a parameter or parameter override. Extending the generate
construct to apply to port lists as well as module bodies seems like a
good way to do this. Here's an example of what I'm proposing:
	
	module foo #(parameter flag=0)
	 ( generate
	     if (flag ==1)
	       input x;
	   endgenerate
	  );
	
	...
	
	endmodule

	I did not submit Mantis 210. I think. To the best of my
recollection, I did not even know about it. But I fully agree with the
need. Both at Freescale and at Intel, the need for conditional (and
multiple) ports has come up time and again. 

	I'd like to solicit thoughts and suggestions that I can work up
into a proposal.

	Thanks,

	Shalom

	 

	Shalom Bresticker

	Intel Jerusalem LAD DA

	+972 2 589-6852

	+972 54 721-1033