[sv-bc] Proposal to make it easier to use packages with port declarations

Several months ago I posted an e-mail regarding a limitation on using
packages with module port declaration, along with a basic proposal on how to
fix the problem. All that is needed is a 1-line change in the BNF, and a
short explanation added to section 18. This limitation was brought to my
attention by a company that was looking at adopting SystemVerilog in their
next design project. I was under the impression that the proposal I had
e-mailed out had been added to the SV errata data base. I was reviewing the
data base for our meeting today, however, and could not find the proposal.

I have attached a PDF file with a more complete, ready to vote on, proposal
for today's meeting. The PDF file also contains a brief explanation of the
limitation.

Once again, can someone please enter this into the SV errata data base for
me? (perhaps the issue is already there, and I just couldn't find it).

Stu
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Stuart Sutherland
stuart@sutherland-hdl.com
+1-503-692-0898