RE: [sv-bc] Proposal to make it easier to use packages with port declarations

Hi,

 

I have the following situation and I am not sure how to handle it. It
may be trivial, but it currently escapes me.

 

I want to declare a module whose ports have parameterized types, and I
want to do it using ANSI-style port declarations.

 

So preceding the port list, I want to have typedefs, and the typedefs
need to be parameterized. I need to be able to override the parameter
values as well.

 

How do I do this?

 

Thanks,

Shalom

 

________________________________

From: owner-sv-bc@server.eda.org [mailto:owner-sv-bc@server.eda.org] On
Behalf Of Brad Pierce
Sent: Friday, May 12, 2006 12:54 AM
To: sv-bc@server.eda.org
Subject: Re: [sv-bc] Proposal to make it easier to use packages with
port declarations

 

Stu,

 

I agree with you that we should strive to make any new syntax look like
Verilog.

 

How would you feel about prepending

 

     [ package_import_list ]  

 

to every occurrence of

 

     [ parameter_port_list ]

 

where

 

    package_import_list ::= 

        import ( [ package_import_item { , package_import_item } ] )

 

? For example,

 

    extern module automatic M 
          import(shared_decls::*, shared_decls2::something)
          #(...)
          (...);

 

-- Brad

 

-----Original Message-----
From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org] On Behalf Of
Stuart Sutherland
Sent: Wednesday, May 10, 2006 10:19 PM
To: sv-bc@eda.org
Subject: RE: [sv-bc] Proposal to make it easier to use packages with
port declarations

 

Brad,

 

I do not have a strong preference for either of the proposed syntax
styles,

though I do have a slight preference to using the already existing V2K

parameter list just because it looks more like Verilog.  The important
thing

to me is the ability to use package definitions in port declarations
without

having to redundantly name the package for each port.  I will leave the

fine-grain details on where semicolons and such are needed to parser

experts.

 

Stu

~~~~~~~~~~~~~~~~~~~~~~~~~

Stuart Sutherland

stuart@sutherland-hdl.com

+1-503-692-0898

  

 

> -----Original Message-----

> From: owner-sv-bc@server.eda.org 

> [mailto:owner-sv-bc@server.eda.org] On Behalf Of Brad Pierce

> Sent: Tuesday, May 09, 2006 2:44 PM

> To: sv-bc@server.eda.org

> Subject: Re: [sv-bc] Proposal to make it easier to use 

> packages with port declarations

> 

> Stu,

> 

> Following up on http://www.eda.org/sv-bc/hm/4402.html , are 

> you still in

> favor of the syntax you proposed in Mantis 329?  (Personally, I'm

> tending to favor the syntax of Gord in

> http://www.eda.org/sv-bc/hm/4408.html .)

> 

> If so, the BNF in the proposal would need to be modified to take into

> account that currently "package_import_declaration" includes its

> terminating semicolon.  The BNF in the proposal would only 

> accept syntax

> like

> 

>    module #(import shared_decls::*; parameter SIZE = 2048)   

> 

> That's OK by me for the reasons in 

> 

>    http://eda.org/svdb/bug_view_page.php?bug_id=922

> 

> but your examples indicate that such semicolon syntax wasn't your

> intent.

> 

> Less importantly, the proposal would need to be updated to reflect the

> clause renumberings, a recent fix to the 

> "parameter_port_list" BNF, and

> perhaps other things.

> 

> Also, there might need to be some restriction on syntax such as

> 

>    module #(import shared_decls::*, SIZE = 2048)

> 

> perhaps requiring that the parameter keyword can only be 

> omitted at the

> start of a parameter port list

> 

>    module #(size = 2048, import shared_decls::*)

> 

> But I haven't thought about that enough to offer an opinion.

> 

> -- Brad

> 

> 

> 

>