Subject: Re: [sv-bc] logic -vs- ulogic
From: Kevin Cameron x3251 (Kevin.Cameron@nsc.com)
Date: Mon Apr 14 2003 - 10:09:53 PDT
> From: "Clifford E. Cummings" <cliffc@sunburst-design.com>
> Subject: [sv-bc] logic -vs- ulogic
>
> Hi, All -
>
> I have raised issue this a number of times. I don't know if it was ever
> formally voted.
>
> I still think if we are going to have these "logic" and "bit" types, that
> we would be doing the Verilog and VHDL communities a favor by at least
> choosing the keywords: ulogic, ubit.
>
> In VHDL, std_logic_type is the resolved type. std_ulogic_type is the
> unresolved type. I don't see a compelling reason to confuse the poor VHDL
> engineers by swapping the definitions on them.
>
> Not only that, but I am guessing the "ulogic" will kill fewer existing
> designs that "logic" (same argument for "ubit" vs. "bit").
>
> This is a relatively easy global change, one that might be less
> controversial when it is addressed by the IEEE VSG.
>
> Thoughts? Is this possible?
>
> Regards - Cliff
> ----------------------------------------------------
> Cliff Cummings - Sunburst Design, Inc.
I agree with Cliff. My personal preference would be to do like VHDL and
have a standard header file that defines logic and bit with typedefs
of a longer named type e.g.:
typedef unresolved_bit bit;
typedef resolved_bit logic;
However I think it would be best left (at this time) for 3.2 along with
abstracting the resolution mechanisms (for user defined types).
Kev.
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