Subject: [sv-bc] logic -vs- ulogic
From: Clifford E. Cummings (cliffc@sunburst-design.com)
Date: Mon Apr 14 2003 - 09:51:20 PDT
Hi, All -
I have raised issue this a number of times. I don't know if it was ever
formally voted.
I still think if we are going to have these "logic" and "bit" types, that
we would be doing the Verilog and VHDL communities a favor by at least
choosing the keywords: ulogic, ubit.
In VHDL, std_logic_type is the resolved type. std_ulogic_type is the
unresolved type. I don't see a compelling reason to confuse the poor VHDL
engineers by swapping the definitions on them.
Not only that, but I am guessing the "ulogic" will kill fewer existing
designs that "logic" (same argument for "ubit" vs. "bit").
This is a relatively easy global change, one that might be less
controversial when it is addressed by the IEEE VSG.
Thoughts? Is this possible?
Regards - Cliff
----------------------------------------------------
Cliff Cummings - Sunburst Design, Inc.
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