Re: [sv-bc] logic -vs- ulogic


Subject: Re: [sv-bc] logic -vs- ulogic
From: Stuart Sutherland (stuart@sutherland-hdl.com)
Date: Mon Apr 14 2003 - 19:58:01 PDT


Cliff,

I'm glad you resurrected your discussion on this. I thought that perhaps
you had abandoned it, or it was discussed and voted out (though I never
noticed a vote in any of the minutes). I am very much in favor of the name
change, for exactly the reasons you mention. The time to change it is
before 3.1 is shipped, not after SV is turned over to the IEEE. Whatever
keyword we select for 3.1 will likely become a de facto standard.

Stu

At 09:51 AM 4/14/2003, Clifford E. Cummings wrote:
>Hi, All -
>
>I have raised issue this a number of times. I don't know if it was ever
>formally voted.
>
>I still think if we are going to have these "logic" and "bit" types, that
>we would be doing the Verilog and VHDL communities a favor by at least
>choosing the keywords: ulogic, ubit.
>
>In VHDL, std_logic_type is the resolved type. std_ulogic_type is the
>unresolved type. I don't see a compelling reason to confuse the poor VHDL
>engineers by swapping the definitions on them.
>
>Not only that, but I am guessing the "ulogic" will kill fewer existing
>designs that "logic" (same argument for "ubit" vs. "bit").
>
>This is a relatively easy global change, one that might be less
>controversial when it is addressed by the IEEE VSG.
>
>Thoughts? Is this possible?
>
>Regards - Cliff
>----------------------------------------------------
>Cliff Cummings - Sunburst Design, Inc.
>14314 SW Allen Blvd., PMB 501, Beaverton, OR 97005
>Phone: 503-641-8446 / FAX: 503-641-8486
>cliffc@sunburst-design.com / www.sunburst-design.com
>Expert Verilog, Synthesis and Verification Training

~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Stuart Sutherland Sutherland HDL Inc.
stuart@sutherland-hdl.com 22805 SW 92nd Place
phone: 503-692-0898 Tualatin, OR 97062
www.sutherland-hdl.com
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