RE: [sv-ec] minor bug in 18.3 example

From: Bresticker, Shalom <shalom.bresticker@intel.com>
Date: Wed Dec 21 2011 - 23:13:27 PST

Thanks, the editor will fix it.

Shalom

From: owner-sv-ec@eda.org [mailto:owner-sv-ec@eda.org] On Behalf Of Radoslaw Nawrot
Sent: Thursday, December 22, 2011 9:10 AM
To: sv-ec@eda.org
Subject: [sv-ec] minor bug in 18.3 example

Hello,

This is my first topic on SV-EC. Heretofor I wrote at SV-CC.
I dont know If such problem was reported but there is a minor bug in 1800-2009 18.3::

class Bus;

rand bit[15:0] addr;

rand bit[31:0] data;

constraint word_align {addr[1:0] == 2'b0;}

endclass

Should be:

class Bus;

rand bit[15:0] addr;

rand bit[31:0] data;

constraint word_align {addr[1:0] == 2'b0;}

endclass

Regards,

Radek

Radoslaw.Nawrot@aldec.com.pl<mailto:Radoslaw.Nawrot@aldec.com.pl>

--
This message has been scanned for viruses and
dangerous content by MailScanner<http://www.mailscanner.info/>, and is
believed to be clean.
---------------------------------------------------------------------
Intel Israel (74) Limited
This e-mail and any attachments may contain confidential material for
the sole use of the intended recipient(s). Any review or distribution
by others is strictly prohibited. If you are not the intended
recipient, please contact the sender and delete all copies.
-- 
This message has been scanned for viruses and
dangerous content by MailScanner, and is
believed to be clean.
Received on Wed Dec 21 23:15:17 2011

This archive was generated by hypermail 2.1.8 : Wed Dec 21 2011 - 23:15:19 PST