RE: [sv-ec] minor bug in 18.3 example

Yes, I will fix this in the next draft.

Stu
~~~~~~~~~~~~~~~~~~~~~~~~~~~
Stuart Sutherland

Sutherland HDL, Inc.

stuart@sutherland-hdl.com

503-692-0898
www.sutherland-hdl.com

From: owner-sv-ec@eda.org [mailto:owner-sv-ec@eda.org] On Behalf Of
Bresticker, Shalom
Sent: Wednesday, December 21, 2011 11:13 PM
To: Radoslaw Nawrot; sv-ec@eda.org
Cc: Stuart Sutherland
Subject: RE: [sv-ec] minor bug in 18.3 example

Thanks, the editor will fix it.

Shalom

From: owner-sv-ec@eda.org [mailto:owner-sv-ec@eda.org] On Behalf Of Radoslaw
Nawrot
Sent: Thursday, December 22, 2011 9:10 AM
To: sv-ec@eda.org
Subject: [sv-ec] minor bug in 18.3 example

Hello,

This is my first topic on SV-EC. Heretofor I wrote at SV-CC.

I dont know If such problem was reported but there is a minor bug in
1800-2009 18.3::

class Bus;

rand bit[15:0] addr;

rand bit[31:0] data;

constraint word_align {addr[1:0] == 2'b0;}

endclass

Should be:

class Bus;

rand bit[15:0] addr;

rand bit[31:0] data;

constraint word_align {addr[1:0] == 2'b0;}

endclass

Regards,

Radek

Radoslaw.Nawrot@aldec.com.pl

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