[sv-ec] minor bug in 18.3 example

Hello,
 
This is my first topic on SV-EC. Heretofor I wrote at SV-CC.
I dont know If such problem was reported but there is a minor bug in
1800-2009 18.3::
 
class Bus;

rand bit[15:0] addr;

rand bit[31:0] data;

constraint word_align {addr[1:0] == 2'b0;}

endclass

Should be:

class Bus;

rand bit[15:0] addr;

rand bit[31:0] data;

constraint word_align {addr[1:0] == 2'b0;}

endclass

Regards,

Radek

Radoslaw.Nawrot@aldec.com.pl

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