RE: [sv-ec] restriction on typedef on net.

> 
> [Yulik] I can easily imagine code like:
> 
> typedef logic [24:0] data_type;
> typedef wire data_type net_type;
> module (output data_type var_sum, output net_type net_sum);
> 
> Why not?
[DR] When you have

typedef integer data_type;
data_type v;
integer x;

The declarations of v and x are really

var data_type v;
var integer x;

The var keyword was made optional to be backward compatible with
Verilog. And as Steven said 

wire [1:2] w;

is really 

wire logic [1:2] w;

for backward compatibility with Verilog as well.

So now you can do

var data_type v;
wire data_type w;

Var and wire are essentially declaring the implementation of a data
type, which affects the resolution a signal in the allowance/presence of
multiple drivers.

But what if you had 

typedef wire logic w1;
typedef struct {logic m1; w1 m2} s_t;

Is 
wire s_t s1; //legal?
var s_t s2; // illegal?

Now what is supposed to be a data type is carrying more information that
gets much more complicated to define in the context of parameterized
data types.

Dave




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