RE: [sv-ec] restriction on typedef on net.

The only complication I see here is that you need to define for each bit
of the data type what net type it is. The current language allows
specification of only one kind of net type for all bits of the "net". If
net type would be allowed as a part of data type, one could specify the
net type for each part of the data type individually, as you have shown
in the example with struct. 

All is needed is to provide a backward compatible definition of how to
calculate the net type of each part of the data type. For example, the
net type specified on the inner part of the type overrides the net type
specification on the outer part. Or vice versa. Or disallowing
specification of more than one net type for each given part of the type.


Once such definition is provided, the language would become more
powerful as it would allow things like:

1. Ability to specify net types in typedefs.
2. Ability to specify net types in type parameters.
3. Ability to specify net types in struct/union members, effectively
allowing specification of different parts of a data entity
(net/variable) as having different net types.

I see net types as just another qualifier on the data types, just like
signedness or packedness qualifiers. Why should language allow
specification of signedness on an individual member of a struct, but not
the net type specification? The recent enhancement of allowing data
types as a part of net declaration is a step in right direction, but it
is not general enough. The life would be much easier for the users if
the concepts of variables and nets, as well as data types and net types,
would be unified. 

--Yulik.

-----Original Message-----
From: Rich, Dave [mailto:Dave_Rich@mentor.com] 
Sent: Friday, December 21, 2007 7:26 PM
To: Feldman, Yulik; Steven Sharp; Bresticker, Shalom;
danielm@aldec.com.pl; sv-ec@server.eda.org; mirekf@aldec.com.pl
Subject: RE: [sv-ec] restriction on typedef on net.

> 
> [Yulik] I can easily imagine code like:
> 
> typedef logic [24:0] data_type;
> typedef wire data_type net_type;
> module (output data_type var_sum, output net_type net_sum);
> 
> Why not?
[DR] When you have

typedef integer data_type;
data_type v;
integer x;

The declarations of v and x are really

var data_type v;
var integer x;

The var keyword was made optional to be backward compatible with
Verilog. And as Steven said 

wire [1:2] w;

is really 

wire logic [1:2] w;

for backward compatibility with Verilog as well.

So now you can do

var data_type v;
wire data_type w;

Var and wire are essentially declaring the implementation of a data
type, which affects the resolution a signal in the allowance/presence of
multiple drivers.

But what if you had 

typedef wire logic w1;
typedef struct {logic m1; w1 m2} s_t;

Is 
wire s_t s1; //legal?
var s_t s2; // illegal?

Now what is supposed to be a data type is carrying more information that
gets much more complicated to define in the context of parameterized
data types.

Dave



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