RE: [sv-ec] restriction on typedef on net.

>2) 'output wire T' still do not allow you to manage the net kinds
globally
>(i.e.: via type parameters) - what if you would like to change the net
kind
>across whole design (or its portion) ? 

This is true (though there is nothing to prevent the addition of
something
like a nettype parameter).  On the other hand, if wire were part of the
data type, it would not be possible to declare a variable and a wire of
the same data type, which would create far more problems.

[Yulik] I can easily imagine code like:

typedef logic [24:0] data_type;
typedef wire data_type net_type;
module (output data_type var_sum, output net_type net_sum);

Why not?
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