RE: [sv-ec] restriction on typedef on net.

>Isn't this:
> 
>typedef reg ... T;
>output wire T ...
> 
>(which virtually expands to:)
> 
>output wire reg ...
> 
>a "visually contradictory"  ?
>(see other thread below ...)

It is enough to make some of us cringe, since we felt that "reg" should
mean what "var" means now, instead of being a synonym for "logic".  But
it is too late for that.



>2) 'output wire T' still do not allow you to manage the net kinds globally
>(i.e.: via type parameters) - what if you would like to change the net kind
>across whole design (or its portion) ? 

This is true (though there is nothing to prevent the addition of something
like a nettype parameter).  On the other hand, if wire were part of the
data type, it would not be possible to declare a variable and a wire of
the same data type, which would create far more problems.

Steven Sharp
sharp@cadence.com


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