Re: [sv-ec] restriction on typedef on net.

>From: "danielm" <danielm@aldec.com.pl>

>Typedef cannot be used to define NET types. This is very inconvienient
>have code like below.

>Port signals like wire [24:0] are widely used in lots of module declaration.

Daniel,

In "wire [24:0]", the data type is not "wire [24:0]".  Instead, it is
implicitly "logic [24:0]".  The declaration is equivalent to
"wire logic [24:0]".  You can use a typedef for the type and then
declare a wire of that type.  So you can write:

typedef logic [24:0] T;
module add_sub (
    input add,
    input sub,
    input wire T fa,
    input wire T fb,
    output wire T sum
    );
    
Or since inputs already default to being wires if not specified:

typedef logic [24:0] T;    
module add_sub (
    input add,
    input sub,
    input T fa,
    input T fb,
    output wire T sum
    );

Notice that if you want the output to be a variable instead, because
you are computing it in an always block, you can just change this to:

typedef logic [24:0] T;    
module add_sub (
    input add,
    input sub,
    input T fa,
    input T fb,
    output var T sum
    );
    
Or since outputs default to being variables if declared with an explicit
type name:


typedef logic [24:0] T;    
module add_sub (
    input add,
    input sub,
    input T fa,
    input T fb,
    output T sum
    );
 

If "wire" were part of the data type, you couldn't do this.  You would
need a different data type for a variable, even though it had the same
width and could take on the same values.  That is why "wire" and "var"
are treated as properties separate from the data type.

Steven Sharp
sharp@cadence.com


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