RE: [sv-ec] restriction on typedef on net.

Isn't this:
 
typedef reg ... T;
output wire T ...
 
(which virtually expands to:)
 
output wire reg ...
 
a "visually contradictory"  ?
(see other thread below ...)
 
 
 
1) 'typedef wire' provide more readable and intuitive syntax
 
2) 'output wire T' still do not allow you to manage the net kinds globally
(i.e.: via type parameters) - what if you would like to change the net kind
across whole design (or its portion) ? 
 
Regards,
Mirek
 

  _____  

From: owner-sv-ec@server.eda.org [mailto:owner-sv-ec@server.eda.org] On
Behalf Of Rich, Dave
Sent: 18 grudnia 2007 10:38
To: Surya Pratik Saha; sv-ec@server.eda.org; sv-bc@server.eda.org
Subject: RE: [sv-ec] 'reg' after net type



[...] 

It also is to encourage people to use logic instead of reg as a data type
because wire reg is visually contradictory to anyone familiar with Verilog.

 

Dave

 

  _____  

From: owner-sv-ec@server.eda.org [mailto:owner-sv-ec@server.eda.org] On
Behalf Of Bresticker, Shalom
Sent: 20 grudnia 2007 13:55
To: danielm; sv-ec@server.eda.org
Subject: RE: [sv-ec] restriction on typedef on net.


Yes.


  _____  

From: danielm [mailto:danielm@aldec.com.pl] 
Sent: Thursday, December 20, 2007 2:53 PM
To: Bresticker, Shalom; sv-ec@server.eda.org
Subject: RE: [sv-ec] restriction on typedef on net.


So can I do :

typedef reg [24:0] T;
module add_sub (   
    output wire T sum
    );
//here signal sum will be visible as a net not as an variable - I will be
abble to have multiple assign to sum
endmodule  
 
DANiel

  _____  

From: Bresticker, Shalom [mailto:shalom.bresticker@intel.com] 
Sent: Thursday, December 20, 2007 12:14 PM
To: danielm; sv-ec@server.eda.org
Subject: RE: [sv-ec] restriction on typedef on net.


typedefs define data types.
 
wire and var are kinds, not data types.
 
Data types are an attribute of a net or a variable.
 
Shalom


  _____  

From: owner-sv-ec@server.eda.org [mailto:owner-sv-ec@server.eda.org] On
Behalf Of danielm
Sent: Thursday, December 20, 2007 1:09 PM
To: sv-ec@server.eda.org
Subject: [sv-ec] restriction on typedef on net.


Typedef cannot be used to define NET types. This is very inconvienient ie we
have code like below.
 
module add_sub (   
    input add,
    input sub,
    input [24:0] fa,
    input [24:0] fb,
    output [24:0] sum
    );  
 
Port signals like wire [24:0] are widely used in lots of module declaration.

It would be nice to can wrtie it like below
typedef wire [24:0] T;
module add_sub (   
    input add,
    input sub,
    input T fa,
    input T fb,
    output T sum
    );  
 
Why LRM dissalows this?
 
DANiel

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