RE: [sv-ec] restriction on typedef on net.

So can I do :
typedef reg [24:0] T;
module add_sub (   
    output wire T sum
    );
//here signal sum will be visible as a net not as an variable - I will be
abble to have multiple assign to sum
endmodule  
 
DANiel

  _____  

From: Bresticker, Shalom [mailto:shalom.bresticker@intel.com] 
Sent: Thursday, December 20, 2007 12:14 PM
To: danielm; sv-ec@server.eda.org
Subject: RE: [sv-ec] restriction on typedef on net.


typedefs define data types.
 
wire and var are kinds, not data types.
 
Data types are an attribute of a net or a variable.
 
Shalom


  _____  

From: owner-sv-ec@server.eda.org [mailto:owner-sv-ec@server.eda.org] On
Behalf Of danielm
Sent: Thursday, December 20, 2007 1:09 PM
To: sv-ec@server.eda.org
Subject: [sv-ec] restriction on typedef on net.


Typedef cannot be used to define NET types. This is very inconvienient ie we
have code like below.
 
module add_sub (   
    input add,
    input sub,
    input [24:0] fa,
    input [24:0] fb,
    output [24:0] sum
    );  
 
Port signals like wire [24:0] are widely used in lots of module declaration.

It would be nice to can wrtie it like below
typedef wire [24:0] T;
module add_sub (   
    input add,
    input sub,
    input T fa,
    input T fb,
    output T sum
    );  
 
Why LRM dissalows this?
 
DANiel

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