RE: [sv-ec] restriction on typedef on net.

I agree with Daniel that it is very unfortunate that the language
doesn't allow net types to be specified in a typedef. If net types would
be considered data types, the language would be much more flexible. Not
only one could use typedefs to make the code shorter and more readable,
it would also be possible to do things like parameterization of modules
(or other design entities) based on net types, using type parameters.
Just a week ago I have a seen a real-life test case, where the designer
wanted to let a port of parameterized module to have different net types
based on the module parameterization, and the inability to parameterize
on net types just made his intention impossible to realize.

 

Theoretically, I don't think there is anything in the language that
prevents net types to be considered a kind of an (extended notion of)
data type. It is just that the language evolved in such a way that
historically nets and their types are treated as something special and
different from variables and the data types.

 

I understand that enhancing the language to treat net types as data
types is not something that can be done right now, but it would be a
very welcome feature for the post-2008 version of the standard.

 

--Yulik.

 

________________________________

From: owner-sv-ec@server.eda.org [mailto:owner-sv-ec@server.eda.org] On
Behalf Of Bresticker, Shalom
Sent: Thursday, December 20, 2007 1:14 PM
To: danielm; sv-ec@server.eda.org
Subject: RE: [sv-ec] restriction on typedef on net.

 

typedefs define data types.

 

wire and var are kinds, not data types.

 

Data types are an attribute of a net or a variable.

 

Shalom

	 

	
________________________________


	From: owner-sv-ec@server.eda.org
[mailto:owner-sv-ec@server.eda.org] On Behalf Of danielm
	Sent: Thursday, December 20, 2007 1:09 PM
	To: sv-ec@server.eda.org
	Subject: [sv-ec] restriction on typedef on net.

	Typedef cannot be used to define NET types. This is very
inconvienient ie we have code like below.

	 

	module add_sub (   
	    input add,
	    input sub,
	    input [24:0] fa,
	    input [24:0] fb,
	    output [24:0] sum
	    );  

	 

	Port signals like wire [24:0] are widely used in lots of module
declaration. 

	It would be nice to can wrtie it like below

	typedef wire [24:0] T;

	module add_sub (   
	    input add,
	    input sub,
	    input T fa,
	    input T fb,
	    output T sum
	    );  

	 

	Why LRM dissalows this?

	 

	DANiel

	
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