RE: [sv-ec] assigning string literal to parameter

>From: "Arturo Salz" <Arturo.Salz@synopsys.com>

>Actually, even Verilog-2001 treats string literals as special, not just
>as integral constants. This difference is visible to the PLI layer,
>which includes the string type. Hence, string literals are handled
>differently by system tasks such $display.

The PLI layer can also distinguish 1+1 from 2 as an argument.  That
does not prevent them from both being integral expressions.

You are right that there are some special situations where string
literals are treated specially, such as being required for formats
in $display.  But for most purposes, they are just integral constants.


> I don't disagree with your
>conclusion that it is legal to assign a string literal to an untyped
>parameter, but there may be some subtleties to work out as to what is
>the type of the parameter.

We don't have to reason based solely on the LRM.  It was legal in the
de facto standard simulator on which the LRM was based, and presumably
all the implementations since then.  We know it is legal and what its
semantics are in Verilog.

There may be some freedom in deciding some of the subtleties for SV,
but not complete freedom.  For anything that was legal in Verilog, it
needs to remain backward compatible.

We know that treating the type as a vector type works, since that is
what Verilog does.  Treating it as the SV string type might work, as
long as that would not change the behavior of any legal Verilog code.

Steven Sharp
sharp@cadence.com