RE: [sv-ec] assigning string literal to parameter

Steve,

Actually, even Verilog-2001 treats string literals as special, not just
as integral constants. This difference is visible to the PLI layer,
which includes the string type. Hence, string literals are handled
differently by system tasks such $display. I don't disagree with your
conclusion that it is legal to assign a string literal to an untyped
parameter, but there may be some subtleties to work out as to what is
the type of the parameter.

	Arturo

-----Original Message-----
From: owner-sv-ec@eda.org [mailto:owner-sv-ec@eda.org] On Behalf Of
Steven Sharp
Sent: Tuesday, November 21, 2006 10:21 AM
To: sv-ec@eda.org; Neil.Korpusik@Sun.com
Cc: yulik.feldman@intel.com
Subject: Re: [sv-ec] assigning string literal to parameter

In Verilog, a string literal is just an integral constant, so it is
perfectly legal to assign to an untyped parameter.

Steven Sharp
sharp@cadence.com