RE: [sv-ec] assigning string literal to parameter

From: Steven Sharp <sharp_at_.....>
Date: Tue Nov 21 2006 - 13:59:19 PST
>From: Steven Sharp <sharp>

>The PLI layer can also distinguish 1+1 from 2 as an argument.  That
>does not prevent them from both being integral expressions.

As a better analogy, I believe the PLI layer can distinguish 32'd1
from 32'h1, even though they are both integral constants with the same
value and have identical behavior in all situations in Verilog.

Steven Sharp
sharp@cadence.com
Received on Tue Nov 21 13:59:26 2006

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