RE: [sv-ec] Coverpoints on nets/wires

This is not an intended limitation. The LRM does state that both
variables and expressions are allowed as coverpoints. Since an integral
net type is an integral expression, it ought to be allowed. But, I agree
that this should be clarified.

 

            Arturo

 

________________________________

From: owner-sv-ec@eda-stds.org [mailto:owner-sv-ec@eda-stds.org] On
Behalf Of Swapnajit Chakraborti
Sent: Wednesday, August 16, 2006 5:55 AM
To: SV_EC List
Subject: [sv-ec] Coverpoints on nets/wires

 

Hi,

 

The LRM mentions that only integral variables can be used as
coverpoints. There is no mention of nets/wires being supported as
coverpoints. Is there any specific reason to exclude nets/wires from
being declared as coverpoints? Or this is just an oversight and we can
probably file a mantis for rectifying this?

 

Regds,

Swapnajit.