RE: [sv-ec] Coverpoints on nets/wires

Added mantis #1575 for this issue.
 
Thx,
Swapnajit.


________________________________

	From: Arturo Salz [mailto:Arturo.Salz@synopsys.com] 
	Sent: Thursday, August 17, 2006 9:07 PM
	To: Swapnajit Chakraborti
	Subject: RE: [sv-ec] Coverpoints on nets/wires
	
	

	Yes. That's the only way it will get fixed. BTW, if you add a
proposal along with the mantis item, it will speedup the process.

	 

	            Arturo 

	 

	
________________________________


	From: Swapnajit Chakraborti [mailto:swapnaj@cadence.com] 
	Sent: Thursday, August 17, 2006 6:52 AM
	To: Arturo Salz
	Subject: RE: [sv-ec] Coverpoints on nets/wires

	 

	So, should I file a mantis for this?

		 

		
________________________________


		From: Arturo Salz [mailto:Arturo.Salz@synopsys.com] 
		Sent: Wednesday, August 16, 2006 10:22 PM
		To: Swapnajit Chakraborti; SV_EC List
		Subject: RE: [sv-ec] Coverpoints on nets/wires

		This is not an intended limitation. The LRM does state
that both variables and expressions are allowed as coverpoints. Since an
integral net type is an integral expression, it ought to be allowed.
But, I agree that this should be clarified.

		 

		            Arturo

		 

		
________________________________


		From: owner-sv-ec@eda-stds.org
[mailto:owner-sv-ec@eda-stds.org] On Behalf Of Swapnajit Chakraborti
		Sent: Wednesday, August 16, 2006 5:55 AM
		To: SV_EC List
		Subject: [sv-ec] Coverpoints on nets/wires

		 

		Hi,

		 

		The LRM mentions that only integral variables can be
used as coverpoints. There is no mention of nets/wires being supported
as coverpoints. Is there any specific reason to exclude nets/wires from
being declared as coverpoints? Or this is just an oversight and we can
probably file a mantis for rectifying this?

		 

		Regds,

		Swapnajit.