RE: [sv-ec] "@ (posedge clk2 && scl_enb && SCL)" Legal clock event?

This is what the 'iff' event operator is supposed to do.

always @ (posedge clk iff signalA) x <=y;

signalA is only evaluated on the posedge of clk


Dave

> -----Original Message-----
> From: owner-sv-ec@eda.org [mailto:owner-sv-ec@eda.org] On Behalf Of
Steven
> Sharp
> Sent: Thursday, November 17, 2005 2:40 PM
> To: sv-ec@eda.org; sv-ac@eda.org; vhdlcohen@aol.com
> Subject: Re: [sv-ec] "@ (posedge clk2 && scl_enb && SCL)" Legal clock
> event?
> 
> 
> > 2. Is is also legal in an always block, i.e.,
> > always @ (posedge clk && signalA) x <=y;
> 
> Yes, this is legal.  Note that it means (posedge (clk && signalA)),
> which waits for a posedge on the value of the expression.  It does not
> mean ((posedge clk) && signalA), which is not valid Verilog.
> 
> I can't comment on what is legal in assertions.
> 
> Steven Sharp
> sharp@cadence.com