[sv-ec] "@ (posedge clk2 && scl_enb && SCL)" Legal clock event?

One tool declares the above clocking expression as illegal. Another 
tool declares it as legal and accepts it.

 "Invalid clocking expression" from vcs (see link below).
 assert property (@ (posedge clk2 && scl_enb && SCL)
 check && SDA==1'b1 ##1 `true [->9] |-> SDA==1'b1
 );
 From VerificationGuild posting
  "Maybe I'm doing something wrong, but the expression @(posedge clk2 && 
scl_enb && SCL) gives me an error message: Invalid clocking expression. 
If I try to make a logical relation in the clocking part, it will give 
this message. I am using the latest vcs. Any idea? "
  
http://verificationguild.com/modules.php?name=Forums&file=viewtopic&p=406
2#4062

  One vendor states that there are no restrictions, other than the 
tools?, on what it can be used as an event expression in an assertion. 
In any case, the variables in the event expression are not sampled 
because they are defining the sampling clock event.

 Two questions:
  1. From an LRM viewpoint is "@ (posedge clk && signalA)" a valid 
expression in an assertion?
 2. Is is also legal in an always block, i.e.,
 always @ (posedge clk && signalA) x <=y;

 For tool compatibility, we cannot have this be a tool dependency.

  
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 Ben Cohen Trainer, Consultant, Publisher (310) 721-4830
 http://www.vhdlcohen.com/ ben_ f rom _abv-sva.org
 * Co-Author: SystemVerilog Assertions Handbook, 2005 ISBN 0-9705394-7-9
  * Co-Author: Using PSL/SUGAR for Formal and Dynamic Verification 2nd 
Edition, 2004, ISBN 0-9705394-6-0
  * Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 
0-9705394-2-8
 * Component Design by Example ", 2001 isbn 0-9705394-0-1
  * VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn 
0-7923-8474-1
  * VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn 
0-7923-8115
  
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