> 2. Is is also legal in an always block, i.e., > always @ (posedge clk && signalA) x <=y; Yes, this is legal. Note that it means (posedge (clk && signalA)), which waits for a posedge on the value of the expression. It does not mean ((posedge clk) && signalA), which is not valid Verilog. I can't comment on what is legal in assertions. Steven Sharp sharp@cadence.comReceived on Thu Nov 17 14:39:47 2005
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